HT56R66/HT56R666
fore entering the Power Down Mode, the wake-up func-
tion of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Low Voltage Detector - LVD
The Low Voltage Detect internal function provides a
means for the user to monitor when the power supply
voltage falls below a certain fixed level as specified in
the DC characteristics.
LVD Operation
The LVD function must be first enabled via a configura-
tion option after which bits 3 and 5 of the RTCC register
are used to control the overall function of the LVD. Bit 3
is the enable/disable control bit and is known as LVDC,
when set low the overall function of the LVD will be dis-
abled. Bit 5 is the LVD detector output bit and is known
as LVDO. Under normal operation, and when the power
supply voltage is above the specified VLVD value in the
DC characteristic section, the LVDO bit will remain at a
zero value. If the power supply voltage should fall below
this VLVD value then the LVDO bit will change to a high
value indicating a low voltage condition. Note that the
LVDO bit is a read-only bit. By polling the LVDO bit in the
RTCC register, the application program can therefore
determine the presence of a low voltage condition.
After power-on, or after a reset, the LVD will be switched
off by clearing the LVDC bit in the RTCC register to zero.
Note that if the LVD is enabled there will be some power
consumption associated with its internal circuitry, how-
ever, by clearing the LVDC bit to zero the power can be
minimised. It is important not to confuse the LVD with
the LVR function. In the LVR function an automatic reset
will be generated by the microcontroller, whereas in the
LVD function only the LVDO bit will be affected with no
influence on other microcontroller functions.
There are a range of voltage values, selected using a
configuration option, which can be chosen to activate
the LVD.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a de-
vice reset when the Watchdog Timer counter overflows.
Watchdog Timer Operation
The Watchdog Timer clock source is provided by the in-
ternal clock, fS, which is in turn supplied by one of two
sources selected by configuration option: fSUB or fSYS/4.
Note that if the Watchdog Timer configuration option
has been disabled, then any instruction relating to its op-
eration will result in no operation.
Most of the Watchdog Timer options, such as en-
able/disable, Watchdog Timer clock source and clear in-
struction type are selected using configuration options.
In addition to a configuration option to enable the Watch-
dog Timer, there are four bits, WDTEN3~ WDTEN0, in
the MISC register to offer an additional enable control of
the Watchdog Timer. These bits must be set to a specific
value of 1010 to disable the Watchdog Timer. Any other
values for these bits will keep the Watchdog Timer en-
abled. After power on these bits will have the disabled
value of 1010.
C L R W D T 1 F la g
C L R W D T 2 F la g
1 o r 2 In s tr u c tio n s
fS Y S /4
W D T O s c illa to r
R T C O s c illa to r
C o n tro l
L o g ic
W D T S o u rc e
C o n fig u r a tio n
fS
O p tio n
8 - b it D iv id e r fS /2 8 7 - b it P r e s c a le r
C LR
¸2
W D T T im e - o u t
(2 13/fS , 2 14/fS , 2 15/fS o r 2 16/fS )
C o n fig O p tio n
fS /2 12, fS /2 13, fS /2 14 o r fS /2 15
Watchdog Timer
Rev. 1.40
83
May 11, 2012