HT66F24D View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F24D' PDF : 177 Pages View PDF
A/D Flash Type 8-bit MCU with EEPROM
HT66F24D/HT66F25D
Entering the SLEEP1 Mode
There is only one way for the device to enter the SLEEP1 Mode and that is to execute the HALT
instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the WDT
or LVD on. When this instruction is executed under the conditions described above, the following
will occur:
• The system clock and Time Base clock will be stopped and the application program will stop at
the HALT instruction, but the WDT or LVD will remain with the clock source coming from the
fLIRC clock.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting as the WDT function is enabled.
• The I/O ports will maintain their present conditions.
In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the
NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to 1
or HLCLK bit is 0 but CKS2~CKS0 is set to 010B, 011B, 100B, 101B, 110B or 111B. As a certain
amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit
is checked. The amount of time required for high speed system oscillator stabilization depends upon
which high speed system oscillator type is used.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the HALT
instruction in the application program with the IDLEN bit in SMOD register equal to 1 and the
FSYSON bit in the CTRL register equal to 0. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the HALT instruction,
but the Time Base clock and fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT function is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the HALT
instruction in the application program with the IDLEN bit in SMOD register equal to 1 and the
FSYSON bit in the CTRL register equal to 1. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock, Time Base clock and fSUB clock will be on and the application program will
stop at the HALT instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT function is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.10
48
March 25, 2013
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