HT66F25D View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F25D' PDF : 177 Pages View PDF
A/D Flash Type 8-bit MCU with EEPROM
HT66F24D/HT66F25D
PDPU Register - HT66F25D only
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
PDPU1 PDPU0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
“—”: Unimplemented, read as 0
PDPUn:
I/O Port D bit n Pull-high Control
0: Disable
1: Enable
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register.
PAWU Register
Bit
7
Name PAWU7
R/W
R/W
POR
0
6
PAWU6
R/W
0
5
PAWU5
R/W
0
4
PAWU4
R/W
0
3
PAWU3
R/W
0
2
PAWU2
R/W
0
1
PAWU1
R/W
0
0
PAWU0
R/W
0
Bit 7~0
PAWU: Port A bit 7 ~ bit 0 Wake-up Control
0: Disable
1: Enable
I/O Port Control Registers
Each I/O port has its own control register known as PAC~PDC, to control the input/output
configuration. With this control register, each CMOS output or input can be reconfigured
dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its
associated port control register. For the I/O pin to function as an input, the corresponding bit of
the control register must be written as 1. This will then allow the logic state of the input pin to be
directly read by instructions. When the corresponding bit of the control register is written as 0, the
I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can
still be used to read the output register. However, it should be noted that the program will in fact
only read the status of the output data latch and not the actual logic status of the output pin.
PAC Register
Bit
Name
R/W
POR
7
PAC7
R/W
1
6
PAC6
R/W
1
5
PAC5
R/W
1
4
PAC4
R/W
1
3
PAC3
R/W
1
2
PAC2
R/W
1
Bit 7~0
PAC7~PAC0: I/O Port A bit 7 ~ bit 0 Input/Output Control
0: Output
1: Input
1
PAC1
R/W
1
0
PAC0
R/W
1
Rev. 1.10
62
March 25, 2013
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