HT66F25D View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F25D' PDF : 177 Pages View PDF
Bit 3
Bit 2
Bit 1
Bit 0
A/D Flash Type 8-bit MCU with EEPROM
HT66F24D/HT66F25D
In the Compare Match Output Mode, the T0IO1 and T0IO0 bits determine how the
TM output pin changes state when a compare match occurs from the Comparator A.
The TM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the TM output
pin should be setup using the T0OC bit in the TM0C1 register. Note that the output
level requested by the T0IO1 and T0IO0 bits must be different from the initial value
setup using the T0OC bit otherwise no change will occur on the TM output pin when
a compare match occurs. After the TM output pin changes state, it can be reset to its
initial level by changing the level of the T0ON bit from low to high.
In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values
of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable
PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is
running
T0OC: TP0_0, TP0_1, TP0_2 output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output
Mode it determines the logic level of the TM output pin before a compare match
occurs. In the PWM Mode it determines if the PWM signal is active high or active
low.
T0POL: TP0_0, TP0_1, TP0_2 output Polarity control
0: Non-invert
1: Invert
This bit controls the polarity of the TP0_0, TP0_1 or TP0_2 output pin. When the bit
is set high the TM output pin will be inverted and not inverted when the bit is zero. It
has no effect if the TM is in the Timer/Counter Mode.
T0DPX: TM0 PWM period/duty Control
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
T0CCLR: Select TM0 Counter clear condition
0: TM0 Comparator P match
1: TM0 Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Compact TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the T0CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The T0CCLR bit is not
used in the PWM Mode.
Rev. 1.10
78
March 25, 2013
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