HYS72T64020GR-3.7-C View Datasheet(PDF) - Infineon Technologies
Part Name
Description
MFG CO.
'HYS72T64020GR-3.7-C' PDF : 33 Pages View PDF
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
6.2 SPD Codes for PC2–3200R (–5)
Product Type
Organization
2 GByte
2 GByte
1 GByte 1 GByte
512 MB
×72
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8)
Label Code
PC2–3200R–333
Jedec SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1 Rev. 1.1
Rev. 1.1
Byte# Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in 80
80
80
80
80
EEPROM
1
Total number of Bytes in
08
08
08
08
08
EEPROM
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses 0E
0E
0E
0E
0E
4
Number of Column Addresses 0B
0B
0B
0A
0A
5
DIMM Rank and Stacking
61
61
60
61
60
Information
6
Data Width
48
48
48
48
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
tCK @ CLmax (Byte 18) [ns]
50
50
50
50
50
10
tAC SDRAM @ CLmax (Byte 18) 60
60
60
60
60
[ns]
11 Error Correction Support (non- 02
02
02
02
02
ECC, ECC)
12 Refresh Rate and Type
82
82
82
82
82
13 Primary SDRAM Width
04
04
04
08
08
14 Error Checking SDRAM Width 04
04
04
08
08
15 Not used
00
00
00
00
00
16 Burst Length Supported
0C
0C
0C
0C
0C
17 Number of Banks on SDRAM 04
04
04
04
04
Device
18 Supported CAS Latencies
38
38
38
38
38
19 Not used
00
00
00
00
00
20 DIMM Type Information
01
01
01
01
01
21 DIMM Attributes
07
07
05
05
04
22 Component Attributes
01
01
01
01
01
23
tCK @ CLmax -1 (Byte 18) [ns] 50
50
50
50
50
24
tAC SDRAM @ CLmax -1 [ns] 60
60
60
60
60
25
tCK @ CLmax -2 (Byte 18) [ns] 50
50
50
50
50
26
tAC SDRAM @ CLmax -2 [ns] 60
60
60
60
60
Data Sheet
Preliminary
23
Rev. 0.85, 2004-04
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