IA188EBPLQ80IR2 View Datasheet(PDF) - InnovASIC, Inc
Part Name
Description
MFG CO.
'IA188EBPLQ80IR2' PDF : 85 Pages View PDF
IA186EB/IA188EB
8-Bit/16-Bit Microcontrollers
Data Sheet
July 10, 2011
Table 8. IA188EB Pin/Signal Descriptions (Continued)
Signal
test_n
txd0
txd1
ucs_n
vcc
vss
wr_n
Name
test_n
txd0
p2.1/txd1
ucs_n
vcc
vss
wr_n
Pin
PLCC LQFP
14
3
52
39
58
45
30
18
1, 23, 11, 29,
42, 64 50, 71
2, 22,
43, 63,
65, 84
5
10, 30,
49, 51,
70, 72
74
PQFP
46
2
8
61
13, 34,
54, 72
12, 14,
33, 35,
53, 73
37
Description
test. Input. Active Low. When the test_n input
is high (i.e., not asserted), it causes the
IA188EB to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
Transmit (tx) data, Serial Port 0. Output. This
pin is the serial data output for Serial Port 0.
During synchronous serial communications,
txd0 becomes the transmit clock (rxd0
functions as an output for data transmission).
Transmit (tx) data, Serial Port 1. Output. This
pin is the serial data output for Serial Port 1.
During synchronous serial communications,
txd1 becomes the transmit clock (rxd1
functions as an output for data transmission).
upper chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
Power (vcc). This pin provides power for the
IA188EB device. It must be connected to a +5V
DC power source.
Ground (vss). This pin provides the digital
ground (0V) for the IA188EB. It must be
connected to a vss board plane.
write. Output. Active Low. When asserted
(low), wr_n indicates that data available on the
data bus are to be latched into the accessed
memory or I/O device.
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