IA8X44PLC44I3 View Datasheet(PDF) - InnovASIC, Inc
Part Name
Description
MFG CO.
'IA8X44PLC44I3' PDF : 65 Pages View PDF
IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
Bit [2]—OPB → (STS.2) Optional poll bit. When set, the SIU will AUTO respond to an
optional poll (UP with P=0). The SIU can set or clear the OPB.
Bit [1]—AM → (STS.1) Auto mode. Dual purpose bit depending upon the setting of bit
NB (SMD.1). If NB is cleared, AM selects the AUTO mode when set, Flexible mode
when clear. If NB is set, AM selects the addressed mode when set and the non-addressed
mode when clear. The SIU can clear AM.
Bit [0]—RBP → (STS.0) Receive buffer protect. When set, prevents writing of data into
the receive buffer. Causes RNR response instead of RR in AUTO mode.
4.10.4 Send/Receive Count Register (NSNR)
Table 34 presents the Send/Receive Count Register, which contains both the transmit and receive
sequence numbers in addition to the tally error indications. The CPU can read and write the STS.
Accessing the STS by the CPU via two cycle instructions—JBC bit,rel and MOV bit,C—should
not be used. The SIU can read and write the NSNR. The NS and NR counters are not used in
non-AUTO mode. NSNR is bit addressable.
Table 34. Send/Receive Count Register
7
6
5
4
3
2
1
0
NS2 NS1 NS0 SES NR2 NR1 NR0 SER
Bit [7]—NS2 → (NSNR.7) Send sequence counter, Bit [2].
Bit [6]—NS1 → (NSNR.6) Send sequence counter, Bit [1].
Bit [5]—NS0 → (NSNR.5) Send sequence counter, Bit [0].
Bit [4]—SES → (NSNR.4) Sequence error send. NR (P) ≠ NS (S) and
NR (P) ≠ NS (S) + 1.
Bit [3]—NR2 → (NSNR.3) Receive sequence counter, Bit [2].
Bit [2]—NR1 → (NSNR.2) Receive sequence counter, Bit [1].
Bit [1]—NR0 → (NSNR.1) Receive sequence counter, Bit [0].
Bit [0]—SER → (NSNR.0) Sequence error receive. NS (P) ≠ NR (S).
®
IA211010112-04
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 39 of 65
1-888-824-4184
Share Link: 
