IC62VV5128LL-100T View Datasheet(PDF) - Integrated Circuit Solution Inc

Part Name

Description

MFG CO.

IC62VV5128LL-100T

512K x 8 1.8V and LOW VCC CMOS STATIC RAM

Integrated Circuit Solution Inc 

1 2 3 4 5 6 7 8 9 10

IC62VV5128L

IC62VV5128LL

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)

Symbol Parameter

-55

-70

-100

Min. Max.

Min. Max.

Min. Max

Unit

tWC Write Cycle Time

tSCE CE to Write End

55 —

70 —

100 —

ns

50 —

65 —

80 —

ns

tAW Address Setup Time to Write End

50 —

65 —

80 —

ns

tHA

Address Hold from Write End

0—

0—

0—

ns

tSA

Address Setup Time

tPWE WE Pulse Width

0—

0—

0—

ns

45 —

55 —

80 —

ns

tSD

Data Setup to Write End

25 —

30 —

40 —

ns

tHD

tHZWE(3)

tLZWE(3)

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

0—

0—

0—

ns

— 30

— 30

— 40

ns

5—

5—

5—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output loading specified in

Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

AC WAVEFORMS

WRITE CYCLE NO. 1 (CE Controlled)

ADDRESS

CE

WE

DOUT

DIN

tWC

tSCE

tHA

tAW

tPWE

tSA

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

8

Integrated Circuit Solution Inc.

LPSR020-0A 11/26/2001

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