Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS810001-21
FEMTOCLOCKS™ DUAL VCXO VIDEO PLL
TABLE 3A. FIRST FREQUENCY TRANSLATION STAGE: VCXO PLL
VCXO PLL Divider Look-Up Table
V3:V0 Pins P Value
M Value
0000
1000
1000
0001
1001
1000
0010
11000
4004
0011
11011
4000
0100
11000
4000
0101
4004
4004
0110
4004
4000
0111
1000
1001
1000
250
91
1001
253
92
1010
92
92
1011
1
600
1100
1
800
1101
1
1728
1110
1
1716
1111
1
960
Video Clock Application
Input (kHz/MHz)
VCXO (MHz)
27MHz
27MHz
27MHz
26.973MHz
74.175MHz
27MHz
74.25MHz
26.973MHz
74.25MHz
27MHz
27MHz
27MHz
27MHz
26.973MHz
26.973MHz
27MHz
74.175MHz
27MHz
74.25MHz
27MHz
27MHz
45kHz
(720P/60 hsync)
33.75kHz
(1080I/60 hsync)
15.625kHz
(PAL hsync)
15.734kHz
(NTSC hsync)
28.125kHz
(1080I/50 hsync)
27MHz
27MHz
27MHz
27MHz
27MHz
27MHz
Alternate Video Clock Application
Input (kHz/MHz) VCXO (MHz)
26.973MHz
26.973MHz
26.973MHz
26.973MHz
26.973MHz
44.955kHz
(720P/59.94)
33.716kHz
(1080I/59.94)
26.973MHz
26.973MHz
26.973MHz
TABLE 3B. SECOND FREQUENCY TRANSLATION STAGE: FEMTOCLOCK MULTIPLIER
FemtoClock Look-Up Table
MF, N1:N0 Pins
FB Div
Out Div
0, 00
22
4
0, 01
22
8
0, 10
22
12
0, 11
22
18
1, 00
24
4
1, 01
24
8
1, 10
24
12
1, 11
24
18
Video Clock Application
VCXO (MHz) Q (MHz)
27MHz
148.5MHz
27MHz
74.25MHz
27MHz
27MHz
54MHz
36MHz
Alternate Video Clock Application
VCXO (MHz)
Q (MHz)
26.973MHz
148.35MHz
26.973MHz
74.175MHz
TABLE 3C. BYPASS FUNCTION TABLE
nBP1
0
0
1
1
Inputs
nBP0
0
1
0
1
Operation
Bypass Frequency Translator PLL and Output Divider
Test Mode: Bypass VCXO Jitter Attenuation PLL and Frequency Translator PLL
LC Mode: Bypass VCXO Jitter Attenuation PLL
PLL Mode: Active
810001BK-21
www.icst.com/products/hiperclocks.html
REV. A AUGUST 12, 2005
4