Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ICS1522 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
MFG CO.
'ICS1522' PDF : 13 Pages View PDF
Prev 11 12 13
ICS1522
Memory Definition
ICS1522 memory is loaded serially with the least significant bit clocked into the device first. After the R/Wn bit, the next
three bits of the programming word (15 bits) hold the memory location to be loaded. The least significant 11 bits are the
data to be loaded (see Timing Diagram).
MEMORY
ADDRESS
DATA BITS
000
0-10
001
0-7
001
8-10
010
0-7
010
8-10
011
0-9
011
10
100
0-2
100
3-5
100
6
100
7
100
8
DEFAULT
VALUES
(HEX)
04F
03
0
06
0
013
0
4
3
1
1
1
100
9
0
100
10
1
101
0
1
101
1
0
101
2
0
101
3
0
101
4-5
0
101
6-7
3
101
8
1
101
9
0
101
10
1
110
0-2
7
110
3
0
110
4
0
110
5
0
110
6
1
110
7
0
110
8
0
110
9
0
110
10
0
NAME
DESCRIPTION
F(0:10)
LO(0:7)
A
HI(0:7)
A
R(0:9)
REF
VCO(0:2)
PFD(0:2)
PDEN
INT_FLT
INT_VCO
CLK_SEL
Reserved
FBK_SEL
FBK_POL
ADD
SWLW
PDA(0:1)
PDB(0:1)
LD_LG
F_EN
Reserved
L(0:2)
OMUX1
OMUX2
OMUX3
OMUX4
DACRST
AUXEN
AUXCLK
EXTREF
Feedback Divider Modulus (Modulus = Value +1)
M Counter Lo Sync State
Don't Care
M Counter Hi Sync State
Don't Care
Reference Divider Modulus (Modulus = Value + 1)
POL External Reference Polarity (1 =Invert)
VCO Gain
Phase Detector Gain
Phase Detector Enable (1 =Enable)
Internal Loop Filter (1 = Internal)
Internal VCO (1 = Internal)
Internal feedback input clock select
(0 = VCO Output)
Reserved - Set to One
Feedback Select (1 =Internal)
External Feedback Polarity (1 =Invert)
Addition of 1 VCO Cycle (0 to 1 = Add)
Removal of 1 VCO Cycle (0 to 1 = Swallow)
Output Post-Scaler
Feedback Post-Scaler
Fine Phase Adj. Lead/Lag (1=Lead)
Fine Phase Adj. Enable (1=Enable)
Reserved - Set to One
Load Counter
OUT1 Select (0 = Load Cntr, 1 = Div By 4 0Deg)
OUT2 Select (0 = Int Fbk, 1 = Div By 4 90Deg)
OUT3 Select (0 = Sync Lo, 1 = Div By 4 180Deg)
OUT4 Select (0 = Sync Hi, 1 = Div By 4 270Deg)
Output Reset (CLK+ = 1, CLK- = 0)
Output Test Mode (1 = Test, See Board Test Support)
Output Clock When in Test Mode
XTAL/EXTREF Input Buffer (1=EXTREF)
12
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]