ICS1522M View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
ICS1522M
Integrated Circuit Systems
'ICS1522M' PDF : 13 Pages View PDF
ICS1522
Pixel-by-Pixel Adjustment of
Genlocking Phase (ICS1522 Application)
To understand the operation of the pixel-by-pixel phase
adjust-ment feature, imagine that the modulus of the on-
chip divider is equivalent to the graphics system overall
divide. Also, imagine that the overflow of the internal
divider occurs at the same time as the overflow of the
graphics system line counter. Initial synchronization is
accomplished by switching from the external feedback
source (graphics system HSYNC) to the internal feedback.
Let us assume that we are now using the internal divider.
Now, imagine that the programmed value of the divider
(really a prescaler) is increased by one for a single pass-
through that prescaler (think of this as “swallowing” a
feedback pulse). We will lose exactly one CLK period of
phase in the feedback path. The VCO will speed up
momentarily to compensate for that, and re-lock the loop.
In doing so, the graphics system will receive exactly one
extra CLK cycle, advancing the phase of the graphics
system HSYNC by one CLK period relative to the reference
HSYNC. In a similar fashion, we can decrease the
programmed value of the prescaler (“adding” a pulse) to
retard the phase of the graphics system. Additionally, sub-
pixel phase adjustment is provided through varying the
voltage at the FINE input pin.
24-Pin SOIC Package
Ordering Information
ICS1522M
Example:
ICS XXXX M
Package Type
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS=Standard Device
ICS reserves the right to make changes in the device data identified in this publication
13 without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
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