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ICS1892Y-10 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
MFG CO.
ICS1892Y-10
ICST
Integrated Circuit Systems ICST
'ICS1892Y-10' PDF : 148 Pages View PDF
ICS1892
Chapter 9 Pin Diagram, Listings, and Descriptions
Table 9-5. Configuration Pins (Continued)
Pin
Name
Pin
Pin
Number Type
Pin Description
DPXSEL
24 Input or Half-Duplex / Full-Duplex Select.
Output The ‘Pin Type’ for this pin depends on the setting for the HW/SW pin
(pin 23). When the HW/SW pin is set for:
Hardware mode, this pin acts as an input. In this case, when the
signal on this pin is logic:
– Low, this pin selects half-duplex operations.
– High, this pin selects full-duplex operations.
Software mode, this pin acts as an output that indicates the current
status of this pin. In this case, when the signal on this pin is logic:
– Low, this pin indicates that it is set for half-duplex operations.
– High, this pin indicates that it is set for full-duplex operations.
HW/SW
23
Input Hardware/Software (Select).
When the signal on this pin is logic:
Low, this pin selects Hardware mode operations.
High, this pin selects Software mode operations.
LOCK
27
Output (Stream Cipher) Lock (Acquired).
When the signal on this pin is logic:
Low, the ICS1892 does not have a lock on the data stream.
High, the 1892 has a lock on the data stream.
LSTA
21
Output Link Status.
This pin is used to report the status of the link segment. When the
signal on this pin is logic:
Low, there is no link established.
High, there is a link established.
This pin is mapped according to the interface for which the ICS1892 is
mapped. For the:
Media Independent Interface (MII), the LSTA is mapped as LSTA.
100M Symbol Interface, the LSTA is mapped as SD.
10M Serial Interface, the LSTA is mapped as LSTA.
Link Pulse Interface, the LSTA is mapped as SD.
MII/SI
19
Input Media Independent Interface / Stream Interface (Select).
This pin is used in combination with the 10/LP and 10/100SEL pins to
configure the ICS1892 MAC/Repeater Interface. When the signal on
this pin is logic:
Low, this pin configures the MAC/Repeater Interface as a Media
Independent Interface.
High, this pin configures the MAC/Repeater Interface as a Stream
Interface.
NOD/REP
1
Input
Node/Repeater (Select).
This selection on this pin affects both the SQE test and the Carrier
Sense (CSR) signal. When the signal on this pin is logic:
Low, this pin enables the ICS1892 to default to node operations.
High, this pin enables the ICS1892 to default to repeater
operations.
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
107
February 26, 2001
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