ICS1893AGLF View Datasheet(PDF) - Integrated Circuit Systems
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MFG CO.
'ICS1893AGLF' PDF : 135 Pages View PDF
ICS1893AG Data Sheet - Preliminary
Chapter 3 Typical ICS1893AG Applications
Chapter 3 Typical ICS1893AG Applications
3.1 Typical ICS1893AG Applications
The ICS1893AG is configured for the majority of single Phy Ethernet applications. These applications
include Network Interface Cards, PC Motherboards, Printers, ACR Riser cards, Set top Boxes, and Game
machines.
Virtually any single Phy application utilizing the standard IEEE MII interface can use the ICS1893AG. The
ICS1893AG offers the same high performance at a lower cost.
3.2 ICS1893AG Features
• The same silicon die is used in the ICS1893AG and ICS1893AF
– Only the package type is different.
• The ICS1893AG offers the same.35µ 3.3V low power operation.
• Parametric specifications and timing diagrams are the same as ICS1893AF and ICS1893Y-10.
• The ICS1893AG incorporates Digital Signal Processing in their PMD Sub layer, thereby allowing them to
transmit and receive data with Unshielded Twisted Pair (UTP) Category 5 cables up to 150 meters in
length. In addition, this ICS-patented technology enables the ICS1893AF and ICS1893AG to address
the effects of Baseline Wander correction with UTP cable lengths up to 150m.
• The ICS1893AG uses the same twisted pair transmitter and receive circuits as the ICS1893AF and
therefore the same recommended board layout techniques apply. See Typical Board Layout section.
• Both share improved transmit circuits resulting in a decrease in the magnitude of the 10Base-T harmonic
content generated during transmission (reference ISO/IEC 8802-3: 1993 Clause 8.3.1.3).
• Both use digital PLL technology resulting in lower jitter and improved stability.
• Both seed the transmit stream cipher with the PHY address. This minimizes cross-talk, EMI and noise in
multiple PHY applications.
• The MDIO Maintenance interface with the MDIO and MDC pins along with all internal registers are
preserved in the ICS1893AG. This enables software configuring for FD/HD, 10Base-T, 100Base-TX and
Auto-Negotiation to be configurable by the MDIO maintenance interface. Default setting is
Auto-Negotiation Enable. All register settings are the same as in the ICS1893AF datasheet.
• The ICS1893AG preserves the dual-purpose LED/Phy Address control pins as in the ICS1893AF. The
captured address seeds the scrambler for lower EMI in for multiple Phy applications.
• All Auto-Negotiation features are preserved in the ICS1893AG. The reset default mode is A_N enabled.
The A_N parallel detect feature is preserved for legacy interoperability.
• Both support the Auto-Negotiation Next Page functions as described in IEEE Std 802.3u-1995 clause
28.2.3.4.
• Both support Management Frame (MF) Preamble Suppression.
ICS1893AG, Rev A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
14
April, 2005
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