ICS1893AGLF View Datasheet(PDF) - Integrated Circuit Systems
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MFG CO.
'ICS1893AGLF' PDF : 135 Pages View PDF
ICS1893AG Data Sheet - Preliminary
Chapter 7 Functional Blocks
7.1 Functional Block: Media Independent Interface
All ICS1893AG MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the
ICS1893AG MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz
(for 10Base-T operations).
The Media Independent Interface (MII) consists of two primary components:
1. An interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893AG).
This MAC-PHY part of the MII consists of three subcomponents:
a. A synchronous Transmit interface that includes the following signals:
(1) A data nibble, TXD[3:0]
(2) An error indicator, TXER
(3) A delimiter, TXEN
(4) A clock, TXCLK
b. A synchronous Receive interface that includes the followings signals:
(1) A data nibble, RXD[3:0]
(2) An error indicator, RXER
(3) A delimiter, RXDV
(4) A clock, RXCLK
c. A Media Status or Control interface that consists of a Carrier Sense signal (CRS) and a Collision
Detection signal (COL).
2. An interface between the PHY (the ICS1893AG) and an STA (Station Management entity). The
STA-PHY part of the MII is a two-wire, Serial Management Interface that consists of the following:
a. A clock (MDC)
b. A synchronous, bi-directional data signal (MDIO) that provides an STA with access to the
ICS1893AG Management Register set
The ICS1893AG Management Register set (discussed in Chapter 8, “Management Register Set”) consists
of the following:
• Basic Management registers.
As defined in the ISO/IEC 8802-3 standard, these registers include the following:
– Control Register (register 0), which handles basic device configuration
– Status Register (register 1), which reports basic device capabilities and status
• Extended Management registers.
As defined in the ISO/IEC 8802-3 standard, the ICS1893AG supports Extended registers that provide
access to the Organizationally Unique Identifier and all auto-negotiation functionality.
• ICS (Vendor-Specific) Management registers.
The ICS1893AG provides vendor-specific registers for enhanced PHY operations. Among these is the
QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time PHY
information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data with a
single register access.
ICS1893AG, Rev. A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
33
April, 2005
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