ICS1893AGLF View Datasheet(PDF) - Integrated Circuit Systems
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MFG CO.
'ICS1893AGLF' PDF : 135 Pages View PDF
ICS1893AG Data Sheet - Preliminary
Chapter 8 Management Register Set
8.2.8 Duplex Mode (bit 0.8)
This bit provides a means of controlling the ICS1893AG Duplex Mode. Its operation depends on several
other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the
ICS1893AG is configured for:
• Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893AG isolates bit 0.8 and uses the
DPXSEL input pin to establish the Duplex mode for the ICS1893AG. In this Hardware mode:
– Bit 0.8 is undefined.
– The ICS1893AG provides a Duplex Mode Status bit (in the QuickPoll Detailed Status Register, bit
17.14), which always shows the setting of an active link.
• Software mode (that is, the HW/SW pin is logic one), the function of bit 0.8 depends on the
Auto-Negotiation Enable bit, 0.12. When the auto-negotiation process is:
– Enabled, the ICS1893AG isolates bit 0.8 and relies upon the results of the auto-negotiation process
to establish the duplex mode.
– Disabled, bit 0.8 determines the Duplex mode. Setting bit 0.8 to logic:
• Zero selects half-duplex operations.
• One selects full-duplex operations. (When the ICS1893AG is operating in Loopback mode, it
isolates bit 0.8, which has no effect on the operation of the ICS1893AG.)
8.2.9 Collision Test (bit 0.7)
This bit controls the ICS1893AG Collision Test function. When an STA sets bit 0.7 to logic:
• Zero, the ICS1893AG disables the collision detection circuitry for the Collision Test function. In this case,
the COL signal does not track the TXEN signal. (The default value for this bit is logic zero, that is,
disabled.)
• One, as per the ISO/IEE 8802-3 standard, clause 22.2.4.1.9, the ICS1893AG enables the collision
detection circuitry for the Collision Test function, even if the ICS1893AG is in Loopback mode (that is, bit
0.14 is set to 1). In this case, the Collision Test function tracks the Collision Detect signal (COL) in
response to the TXEN signal. The ICS1893AG asserts the Collision signal (COL) within 512 bit times of
receiving an asserted TXEN signal, and it de-asserts COL within 4 bit times of the de-assertion of the
TXEN signal.
8.2.10 IEEE Reserved Bits (bits 0.6:0)
The IEEE reserves these bits for future use. When an STA:
• Reads a reserved bit, the ICS1893AG returns a logic zero.
• Writes to a reserved bit, it must use the default value specified in this data sheet.
The ICS1893AG uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1893AG, an STA must maintain the default value of these bits. Therefore, ICS recommends that during
any STA write operation, an STA write the default value to all reserved bits, even those bits that are Read
Only.
ICS1893AG, Rev. A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
61
April, 2005
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