ICS1893BFILF View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'ICS1893BFILF' PDF : 138 Pages View PDF
ICS1893BF Data Sheet - Release
Chapter 7 Management Register Set
7.11 Register 16: Extended Control Register
Table 7-16 lists the bits for the Extended Control Register, which the ICS1893BF provides to allow an STA
to customize the operations of the device.
Note:
1. For an explanation of acronyms used in Table 7-16, see Chapter 1, “Abbreviations and Acronyms”.
2. During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
Table 7-16. Extended Control Register (register 16 [0x10])
Bit
Definition
When Bit = 0
When Bit = 1
16.15 Command Override Write Disabled
enable
Enabled
16.14 ICS reserved
Read unspecified
Read unspecified
16.13 ICS reserved
Read unspecified
Read unspecified
16.12 ICS reserved
Read unspecified
Read unspecified
16.11 ICS reserved
Read unspecified
Read unspecified
16.10 PHY Address Bit 4
For a detailed explanation of this bit’s operation,
see Section 5.5, “Status Interface”.
16.9 PHY Address Bit 3
For a detailed explanation of this bit’s operation,
see Section 5.5, “Status Interface”.
16.8 PHY Address Bit 2
For a detailed explanation of this bit’s operation,
see Section 5.5, “Status Interface”.
16.7 PHY Address Bit 1
For a detailed explanation of this bit’s operation,
see Section 5.5, “Status Interface”.
16.6 PHY Address Bit 0
For a detailed explanation of this bit’s operation,
see Section 5.5, “Status Interface”.
16.5 Stream Cipher Test Mode Normal operation
Test mode
16.4 ICS reserved
Read unspecified
Read unspecified
16.3 NRZ/NRZI encoding
NRZ encoding
NRZI encoding
16.2 Transmit invalid codes Disabled
Enabled
16.1 ICS reserved
Read unspecified
Read unspecified
16.0 Stream Cipher disable Stream Cipher enabled Stream Cipher disabled
Ac-
cess
RW
RW/0
RW/0
RW/0
RW/0
RO
RO
RO
RO
RO
RW
RW/0
RW
RW
RW/0
RW
SF De- Hex
fault
SC 0
–
–
0
–
0
–
0
–
0
–
– P4RD†
– P3TD†
– P2LI†
– P1CL† –
– P0AC†
–
0
–
–
–
1
8
–
0
–
0
–
0
† The default is the state of this pin at reset.
ICS1893BF, Rev. E, 8/11/09
Copyright © 2009, IDT, Inc.
All rights reserved.
76
August, 2009
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