ICS1893BYI-10LF View Datasheet(PDF) - Integrated Circuit Systems
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Description
MFG CO.
'ICS1893BYI-10LF' PDF : 143 Pages View PDF
ICS1893BY-10 Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.16 100M Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion
Table 9-23 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The
time periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• CRS
• COL
Figure 9-17 shows the timing diagram for the time periods.
Table 9-23. 100M MDI Input-to-Carrier Assertion/De-Assertion Timing
Time
Period
Parameter
Conditions
t1 First Bit of /J/ into TP_RX to CRS Assert †
–
t2 First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert †
Half-Duplex Mode
t3 First Bit of /T/ into TP_RX to CRS
–
De-Assert ‡
t4 First Bit of /T/ Received into TP_RX to
COL De-Assert ‡
Half-Duplex Mode
Min.
10
9
13
13
Typ.
–
–
–
–
Max. Units
14 Bit times
13 Bit times
18 Bit times
18 Bit times
† The IEEE maximum is 20 bit times.
‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 9-17. 100M MDI Input to Carrier Assertion / De-Assertion Timing Diagram
First bit
First bit of /T/
TP_RX†
t3
t1
CRS
COL
t2
t4
† Shown
unscrambled.
ICS1893BY-10 Rev A 3/24/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
134
March, 2004
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