ICS1893CFILF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS1893CFILF' PDF : 126 Pages View PDF
ICS1893CF Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.16 Reset: Hardware Reset and Power-Down
Table 9-23 lists the significant time periods for the hardware reset and power-down reset. The time periods
consist of timings of signals on the following pins:
• REF_IN
• RESETn
• TXCLK
Figure 9-17 shows the timing diagram for the time periods.
Table 9-23. Hardware Reset and Power-Down Timing
Time
Period
Parameter
t1 RESETn Active to Device Isolation and Initialization
t2 Minimum RESETn Pulse Width
t3 RESETn Released to TXCLK Valid
Condi-
tions
–
–
–
Min. Typ. Max. Units
– 60 –
ns
500 40 –
ns
– 35 500 ms
Figure 9-17. Hardware Reset and Power-Down Timing Diagram
REF_IN
RESETn
t1
t2
t3
TXCLK Valid
Power
Consumption
(AC only)
ICS1893CF, Rev. F, 03/01/07
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
118
Mar. 2007
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