ICS1893CY-10LF View Datasheet(PDF) - Integrated Circuit Systems

Part Name

Description

MFG CO.

ICS1893CY-10LF

3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

Integrated Circuit Systems 

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ICS1893CY-10 - Release

Chapter 5 Interface Overviews

5.7 Configuration Interface

The following Configuration and Status Interface pins allow the ICS1893CY-10 to be completely configured

and controlled in hardware mode:

• 10/100SEL

• ANSEL

• DPXSEL

• HW/SW

• MII/SI

• NOD/REP

• RESETn

• RXTRI

These pins allow the ICS1893CY-10 to accommodate the following:

• 10M or 100M operations

• Four MAC/Repeater Interface configurations:

– 10M MII

– 100M MII

– 100M Symbol

– 10M Serial

• Node or repeater applications

• Full-duplex or half-duplex data links

In addition to the ISO/IEC-specified, MII control signals, the ICS1893CY-10 provides RXTRI, which is a

tri-state enable pin for the MII receive data path. When this pin is active (that is, a logic one), the following

pins are tri-stated:

• RXCLK

• RXD[3:0]

• RXDV

• RXER

Functionally, the RXTRI pin affects the MII receive channel in the same way as the Control Register’s

isolate bit, bit 0.10. (The isolate bit also affects the transmit data path.) The ICS1893CY-10 can tri-state

these seven signals for all five types of MAC/Repeater Interface configurations, not just the MII interface.

ICS1893CY-10 Rev 1/07

Copyright © 2007, Integrated Device Technology, Inc.

All rights reserved.

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