ICS1893CY-10LF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS1893CY-10LF' PDF : 143 Pages View PDF
ICS1893CY-10 - Release
Chapter 7 Management Register Set
7.14 Register 19: Extended Control Register 2
The Extended Control Register provides more refined control of the internal ICS1893CY-10 operations.
Note:
1. For an explanation of acronyms used in Table 7-20, see Chapter 1, “Abbreviations and Acronyms”.
2. During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
Table 7-21. Extended Control Register (register [0x13])
Bit
Definition
When Bit = 0
When Bit = 1
19.15 Node Mode
19.14 Hardware/Software
Mode
19.13 Remote Fault
19.12 ICS reserved
19.11 ICS reserved
19.10 ICS reserved
19.9 AMDIX_EN
19.8 MDI_MODE
19.7 Twisted Pair Tri-State
Enable, TPTRI
19.6 ICS reserved
19.5 ICS reserved
19.4 ICS reserved
19.3 ICS reserved
19.2 ICS reserved
19.1 ICS reserved
19.0 Automatic 100Base-TX
Power Down
Node mode
Hardware mode
Repeater mode
Software mode
No faults detected
Read unspecified
Read unspecified
Read unspecified
See Table 7-22
See Table 7-22
Twisted Pair Signals
are not Tri-Stated or
No effect
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Do not automatically
power down
Remote fault
detected
Read unspecified
Read unspecified
Read unspecified
See Table 7-22
See Table 7-22
Twisted Pair
Signals are
Tri-Stated
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Power down
automatically
Ac-
cess
RO
RO
SF De- Hex
fault
–
0
4
–
1
RO
–
0
RW
–
0
RW
–
0
2
RO
–
0
RW
–
1
RW
–
0
RW
–
0
0
RW
–
0
RW
–
0
RW
–
0
RW
–
0
1
RW
–
0
RW
–
0
RW
–
1
• † The default is the state of this pin at reset.
ICS1893CY-10 Rev 1/07
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
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