ICS1893CYI-10LF View Datasheet(PDF) - Integrated Circuit Systems
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Description
MFG CO.
'ICS1893CYI-10LF' PDF : 143 Pages View PDF
ICS1893CY-10 - Release
Chapter 6 Functional Blocks
6.6 Functional Block: Management Interface
As part of the MAC/Repeater Interface, the ICS1893CY-10 provides a two-wire serial management
interface which complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This
interface is used to exchange control, status, and configuration information between a Station Management
entity (STA) and the physical layer device (PHY). The PHY and STA exchange this data through a
pre-defined set of management registers. The ISO/IEC standard specifies the following components of this
serial management interface:
• A set of registers (Section 6.6.1, “Management Register Set Summary”)
• The frame structure (Section 6.6.2, “Management Frame Structure”)
• The protocol
In compliance with the ISO/IEC specification, the ICS1893CY-10 implementation of the serial management
interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the
exchange of data. These pins remain active in all ICS1893CY-10 MAC/Repeater Interface modes (that is,
the 10/100 MII, 100M Symbol, and 10M Serial interface modes).
6.6.1 Management Register Set Summary
The ICS1893CY-10 implements a Management Register set that adheres to the ISO/IEC standard. This
register set (discussed in detail in Chapter 7, “Management Register Set”) includes the mandatory ‘Basic’
Control and Status registers and the ISO/IEC ‘Extended’ registers as well as some ICS-specific registers.
6.6.2 Management Frame Structure
The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the
exchange of configuration, control, and status data between a PHY, such as an ICS1893CY-10, and an
STA. All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA
exchange data through a pre-defined register set.
The ICS1893CY-10 complies with the ISO/IEC defined Management Frame Structure and protocol. This
structure supports both read and write operations. Table 6-2 summarizes the Management Frame
Structure.
Note: The Management Frame Structure starts from and returns to an IDLE condition. However, the IDLE
periods are not part of the Management Frame Structure.
Table 6-2. Management Frame Structure Summary
Acronym
PRE
SFD
OP
PHYAD
REGAD
TA
DATA
Frame Field
Frame Function
Preamble (Bit 1.6)
Start of Frame
Operation Code
PHY Address (Bits 16.10:6)
Register Address
Turnaround
Data
Data
Comment
11..11
32 ones
01
2 bits
10/01 (read/write) 2 bits
AAAAA
5 bits
RRRRR
5 bits
Z0/10 (read/write) 2 bits
DDD..DD
16 bits
ICS1893CY-10 Rev 1/07
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
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