ICS514M View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS514M' PDF : 4 Pages View PDF
ICS514
LOCO™ PLL Clock Generator
Pin Assignment
X1/ICLK 1
VDD 2
GND 3
REF 4
8 X2
7 S1
6 S0
5 CLK
Clock Decoding Table (MHz) with
14.31818MHz Crystal or Clock Input
S1 S0
CLK
Multiplier Accuracy
0 0 Power Down CLK -
-
01
25
1.746
1 ppm
M0
33.33
2.328 0.008%
M1
40
2.794
1 ppm
10
50
3.492
1 ppm
11
66.66
4.656 0.008%
0 = connect directly to ground.
1 = connect directly to VDD.
M = leave unconnected (floating).
CLK and REF stop low in power down state.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
X1/ICLK
VDD
GND
REF
CLK
S0
S1
X2
Type
I
P
P
O
O
TI
TI
O
Description
Crystal connection to 14.31818 MHz crystal or clock input.
Connect to +3.3V or +5V.
Connect to ground.
Reference 14.31818 MHz crystal oscillator buffered clock output.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float. See table above.
Select 1 for output clock. Connect to GND or VDD or float. See table above.
Crystal connection to 14.31818 MHz crystal. Leave unconnected for clock input.
Key: I = Input, TI = Tri-Level Input, O = output, P = power supply connection
Notes: 1. With S1 = S0 = 0, the internal PLL is turned off and the CLK output stops low.
The crystal oscillator and REF output are still active.
2. With a clock input, the phase relationship between the input and output clocks can
change each time the device is powered on. If a fixed phase relationship is required,
please use our ICS571 or other zero delay multipliers.
MDS 514 B
2
Revision 080699
Printed 11/13/00
Integrated Circuit Systems • 525 Race Street • San Jose•CA • 95126 • (408)295-9800tel• (408)295-9818fax
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