ICS525-01RILF View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'ICS525-01RILF' PDF : 9 Pages View PDF
ICS525-01/02
OSCaRTM User Configurable Clock
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Output Clock Duty Cycle, OD =
2, 4, 6, 8, or 10
at VDD/2
45
49 to
51
55
%
Output Clock Duty Cycle, OD =
3, 5, 7, or 9
at VDD/2
40
60
%
Output Clock Duty Cycle, OD =
1 (-02 only)
at VDD/2
35
65
Power-down Time, PD low to
clocks stopped
50
ns
Power-up Time, PD high to
clocks stable
10
ms
Absolute Clock Period Jitter,
ICS525-01, Note 2
tja Deviation from mean
±140
ps
One Sigma Clock Period Jitter,
ICS525-01, Note 2
tjs One Sigma
45
ps
Absolute Clock Period Jitter,
ICS525-02, Note 2
tja Deviation from mean
±85
ps
One Sigma Clock Period Jitter,
ICS525-02, Note 2
tjs
One Sigma
30
ps
NOTE 1: Phase relationship between input and output can change at power-up. For a fixed phase
relationship, see the ICS527.
NOTE 2: For 16 MHz, 100 MHz output. Use the -02 for lowest jitter.
MDS 525-01/02 R
7
Integrated Device Technology, Inc. ● www.idt.com
Revision 021710
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