ICS527R-01 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS527R-01' PDF : 8 Pages View PDF
Pin Assignment
R5 1
R6 2
DIV2 3
S0 4
S1 5
VDD 6
ICLK 7
FBIN 8
GND 9
OECLK2 10
2XDRIVE 11
F0 12
F1 13
F2 14
28 R4
27 R3
26 R2
25 R1
24 R0
23 VDD
22 CLK1
21 CLK2
20 GND
19 PDTS
18 F6
17 F5
16 F4
15 F3
ICS527-01
Clock Slicer™
User Configurable Zero Delay Buffer
Frequency Configuration Table
S1
pin 5
0
0
1
1
S0
pin 4
0
1
0
1
CLK1 Output Frequency (MHz)
0 to 70°
-40 to 85°
37 - 75
35 - 70
18 - 37
16 - 35
4 - 10
4-8
75 - 160
70 - 140
To cover the range from 10-18 MHz (0-70 °C) and 8-16
(-40-85°C), select address 01 to generate 2x your desired output
frequency, then configure CLK2 to generate CLK1/2
CLK2 Operation Table
OECLK2
0
1
1
DIV2
X
0
1
CLK2
Z
SYNC
CLK1/2
Clock Drive Select Table
2XDRIVE
0
1
OUTPUT DRIVE
12 mA
25 mA
Pin Description
Pin #
Name
Type Description
1, 2, 24-28 R5, R6, R0-R4 I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 to 127.
3
DIV2
I(PU) Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1. See table above.
4, 5
S0, S1 I(PU) Select pins for output divider determined by user. See table above.
6, 23
VDD
P Connect to VDD.
7
ICLK
I Reference clock input.
8
FBIN
I Feedback clock input.
9, 20
GND
P Connect to ground.
10
OECLK2 I(PU) CLK2 Output Enable. CLK2 tri-stated when low.
11
2XDRIVE I(PU) Clock output drive strength doubled when high.
12-18
F0-F6
I(PU) Feedback divider word input pins determined by user. Forms a binary number from 0 to 127.
19
PDTS I(PU) Power Down. Active low. Turns off entire chip when low. Both Clock outputs tri-stated.
21
CLK2
O Output Clock 2. Can be the SYNC output or a low skew divide by 2 of CLK1.
22
CLK1
O Output Clock 1.
Key: I = Input; I(PU) = Input with internal pull-up resistor; I = Input; O = Output; P = Power supply
connection
MDS 527-01 B
2
Revision 020801
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com
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