ICS527R-02 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS527R-02' PDF : 8 Pages View PDF
Pin Assignment
R5
1
R6
2
D IV 2
3
S0
4
S1
5
VDD
6
P E C LIN
7
P E C LIN
8
GND
9
O E C LK 2
10
F0
11
F1
12
F2
13
F3
14
28
R4
27
R3
26
R2
25
R1
24
R0
23
VDD
22
CLK1
21
CLK2
20
GND
19
PDTS
18
F B IN
17
F6
16
F5
15
F4
28-pin 150 mil body SSOP
ICS527-02
Clock Slicer User Configurable PECL Input Zero Delay Buffer
Output Frequency Range Table
S1 S0
00
01
10
11
Output Frequency (MHz)
Commercial
Industrial
10 - 50
16 - 45
5 - 40
8 - 33
4 - 10
4-8
20 -160
32 - 140
CLK2 Operation Table
OECLK2
0
1
1
DIV2
X
0
1
CLK2
Z
SYNC
CLK1/2
Pin Descriptions
Pin
Number
1,2, 24-28
3
Pin
Name
R5, R6,
R0-R4
DIV2
4, 5
S0, S1
6, 23
7
8
9, 20
10
11-17
VDD
PECLIN
PECLIN
GND
OECLK2
F0-F6
18
FBIN
19
PDTS
21
CLK2
22
CLK1
Pin
Type
Input
Input
Input
Power
Input
Input
Power
Input
Input
Input
Input
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up.
Select pins for output divider determined by user. See table above. Internal
pull-up.
Connect to +3.3 V.
True PECL input clock.
Complementary PECL input clock.
Connect to ground
CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
Feedback clock input
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up.
Output clock 2. Can be SYNC pulse or a low skew divide by 2 of CLK1.
Output clock 1.
MDS 527-02 F
2
Revision 022806
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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