ICS552-03 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS552-03' PDF : 6 Pages View PDF
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
Pin Assignment
OE 1
VDD 2
Q0 3
Q1 4
Q2 5
Q3 6
GND 7
INB 8
16 SELA
15 VDD
14 P3
13 P2
12 P1
11 P0
10 GND
9 INA
16 Pin 173 Mil (0.65mm) TSSOP
Input Source Select
SELA
0
1
Input
INB
INA
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
OE
VDD
Q0
Q1
Q2
Q3
GND
INB
INA
GND
P0
P1
P2
P3
VDD
SELA
Pin
Type
Input
Power
Output
Output
Output
Output
Power
Input
Input
Power
Output
Output
Output
Output
Power
Input
Pin Description
Output Enable. Tri-states outputs when low.Internal Pull-up resistor
Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 15
Clock Output Q0
Clock Output Q1
Clock Output Q2
Clock Output Q3
Ground
Clock Input B. 5 V tolerant input
Clock Input A. 5 V tolerant input
Ground
Clock Output P0
Clock Output P1
Clock Output P2
Clock Output P3
Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 2
Selects either INA or INB. Internal pull-up resistor
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of
0.01 µF should be connected between VDD on pin 2 and GND on pin 7,and between VDD on pin 15 and
GND on pin 10, as close to the device as possible. A 33 Ω series terminating resistor should be used on
each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the ICS552-03 is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30 Ω series termination
on one output (with 33Ω on the others) will cause at least 15 ps of skew.
MDS 552-03 B
2
Revision 052501
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
Share Link: 
