ICS601-02 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'ICS601-02' PDF : 8 Pages View PDF
ICS601-02
LOW PHASE NOISE CLOCK MULTIPLIER
SYNTHESIZERS
Pin Assignment
Multiplier Select Table
CLK
VDDP
VDD
VDD
VDD
X2
S1
X1/ICLK
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
16-pin SOIC
GND
GND
GND
GND
OE
S0
S3
S2
Pin Descriptions
S3 S2 S1 S0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CLK
Input x4/3
Input x4
Input x25/4
Input x3
Input x7.5
Input x5
Input x6
Input x8
Input x8/3
Input x8
Input x12.5
Input x6
Input x15
Input x10
Input x12
Input x16
0 = connect directly to ground
1 = connect directly to VDD
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
CLK
VDDP
VDD
VDD
VDD
X2
S1
X1/ICLK
S2
S3
S0
OE
GND
GND
GND
GND
Pin
Type
Output
Power
Power
Power
Power
XO
Input
XI
Input
Input
Input
Input
Power
Power
Power
Power
Pin Description
Clock output from VCO. Output frequency equals the input frequency times multiplier.
Supply pin for CLK output buffer. Sets output clock amplitude. Connect to 2.5V or 3.3V.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.
Crystal connection. Connect to a 10-27 MHz fundamental parallel mode crystal, or clock.
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.
Output Enable. Tri-states the output clock when low. Internal pull-up.
Connect to ground.
Connect to ground.
Connect to ground.
Connect to ground.
IDT™ LOW PHASE NOISE CLOCK MULTIPLIER
2
ICS601-02
REV G 051310
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