ICS672-02 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS672-02' PDF : 5 Pages View PDF
ICS672-01/02
QuadraClock™ Quadrature Delay Buffer
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Minimum Typical Maximum Units
Supply voltage, VDD & VDDIO
Referenced to GND
-0.5
Inputs and Clock Outputs
Referenced to GND
-0.5
Electrostatic Discharge
MIL-STD-883
2000
Ambient Operating Temperature
0
Ambient Operating Temperature, Industrial
Available on -02 only
-40
Soldering Temperature
Max of 10 seconds
Junction temperature
Storage temperature
-65
DC CHARACTERISTICS (VDD =VDDIO = 3.3 V unless specified otherwise)
7
V
VDD+0.5 V
V
70
°C
85
°C
260
°C
150
°C
150
°C
Operating Voltage, VDD
3.13
Operating Voltage, VDDIO
2.375
Input High Voltage, VIH, ICLK only
VDD/2+1
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
2
Input Low Voltage, VIL
Output High Voltage, VOH
IOH=-12 mA
2.4
Output Low Voltage, VOL
IOL=12 mA
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDDIO-0.4
Operating Supply Current, IDD (Note 2)
No Load, S1=1, S0=0, S2=0
11
Operating Supply Current, IDD (Note 3)
No Load, S1=1, S0=0, S2=0
22
Short Circuit Current
Each output
±50
Input Capacitance
7
AC CHARACTERISTICS (VDD = VDDIO = 3.3 V unless specified otherwise)
5.50
V
VDD
V
V
VDD/2-1 V
V
0.8
V
V
0.4
V
V
mA
mA
mA
pF
Input Clock Frequency
15
Output Clock Frequency
ICS672-01
15
Output Clock Frequency
ICS672-02
15
Output Clock Rise Time, CL = 15 pF
0.8 to 2.0V
Output Clock Fall Time, CL = 15 pF
2.0 to 0.8V
Output Clock Duty Cycle, VDDIO=3.3V
At VDDIO/2
45
Phased Outputs Accuracy (Note 4)
rising edges at VDDIO/2
-250
Input to Output Skew, ICLK to CLK0 (Note 5)
-300
Maximum Absolute Jitter
Cycle to Cycle Jitter, 15 pF loads
150
MHz
84
MHz
135
MHz
1.5
ns
1.5
ns
50
55
%
250
ps
300
ps
75
ps
150
ps
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With ICLK = 20 MHz, FBCLK to FBIN, all outputs at 40 MHz.
3. With ICLK = 66.5 MHz, FBCLK to FBIN, all outputs at 133 MHz.
4. With CLK0:CLK270 equally loaded, and output frequency > 60 MHz.
5. Rising edge of ICLK compared with rising edge of CLK0, with FBCLK connected to FBIN, 15 pF load on CLK0, and
CLK0 > 60 MHz.
MDS 672-01/02 C
4
Revision 112200
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
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