ICS672M-02 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS672M-02' PDF : 5 Pages View PDF
ICS672-01/02
QuadraClock™ Quadrature Delay Buffer
Pin Assignment
ICS672-01/02
ICLK 1
CLK90 2
CLK180 3
CLK270 4
VDDIO 5
GND 6
GND 7
S0 8
16 FBIN
15 FBCLK
14 CLK0
13 VDD
12 GND
11 VDD
10 S2
9 S1
16 pin narrow (150 mil) SOIC
Output Clock Mode Select Table
S2
S1
S0
Output Clocks
0
0
0 Power Down + Tri State
0
0
1
x1
0
1
0
x2
0
1
1
x3
1
0
0
x4
1
0
1
x5
1
1
0
x6
1
1
1
x0.5
Pin Descriptions
Number
1
2
3
4
5
6, 7, 12
8
9
10
11, 13
14
15
16
Name
ICLK
CLK90
CLK180
CLK270
VDDIO
GND
S0
S1
S2
VDD
CLK0
FBCLK
FBIN
Type
I
O
O
O
P
P
I
I
I
P
O
O
I
Description
Clock Input.
Clock Output (90° delayed from CLK0).
Clock Output (180° delayed from CLK0).
Clock Output (270° delayed from CLK0).
Supply voltage for input and output clocks. Must not exceed VDD.
Connect to ground.
Select input 0. See table above.
Select input 1. See table above.
Select input 2. See table above.
Connect to +3.3 V or +5.0 V.
Clock Output phase aligned to ICLK.
Feedback Clock Output (0° phase shift from CLK0).
Feedback Clock Input. In normal operation, connect to FBCLK
Key: I = Input; O = output; P = power supply connection.
External Components
The ICS672-01/01 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD and GND on pins 11 and 12, VDD and GND
on pins 13 and 12, and VDDIO and GND on pins 5 and 6, as close to the device as possible. A series
termination resistor of 33 Ω may be used close to each clock output pin to reduce reflections.
MDS 672-01/02 C
2
Revision 112200
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
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