ICS8344AY-01 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS8344AY-01' PDF : 16 Pages View PDF
Integrated
Circuit
Systems, Inc.
ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8344-01 is a low voltage, low skew
,&6
fanout buffer and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions from
ICS. The ICS8344-01 has two selectable clock
inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs
can accept most standard differential input levels. The
ICS8344-01 is designed to translate any differential signal
levels to LVCMOS levels. The low impedance LVCMOS out-
puts are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased to
48 by utilizing the ability of the outputs to drive two series
terminated lines. Redundant clock applications can make use
of the dual clock input. The dual clock inputs also facilitate
board level testing. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin. The
outputs are driven low when disabled. The ICS8344-01 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and
2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
FEATURES
• 24 LVCMOS outputs, 7Ω typical output impedance
• 2 selectable CLKx, nCLKx inputs
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following input levels: LVDS, LVPECL, LVHSTL, SSTL,
HCSL
• Output frequency up to 250MHz
• Translates any single ended input signal to LVCMOS with
resistor bias on nCLK input
• Synchronous clock enable
• Output skew: 200 ps (maximum)
• Part-to-part skew: 900ps (maximum)
• Bank skew: 85ps (maximum)
• Propagation delay: 5ns (maximum)
• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_SEL
CLK0
nCLK0
1
CLK1
0
nCLK1
CLK_EN
OE
LE
Q
nD
PIN ASSIGNMENT
Q0 - Q7
Q8 - Q15
Q16 - Q23
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
7
ICS8344-01 31
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
48-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
8344AY-01
www.icst.com/products/hiperclocks.html
1
REV. B AUGUST 6, 2001
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