ICS8344AYI-01 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

ICS8344AYI-01

LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

Integrated Device Technology 

1 2 3 4 5 6 7 8 9 10 Next

ICS8344I-01

LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

PRELIMINARY

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5% OR 2.5V ± 5%, OR VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%;

TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

I

IH

Input

nCLK0, nCLK1

High Current CLK0, CLK1

VDD = VIN = 3.465V or 2.625V

VDD = VIN = 3.465V or 2.625V

5

µA

150

µA

IIL

Input

nCLK0, nCLK1 VDD = 3.465V or 2.625V, VIN = 0V

Low Current CLK0, CLK1

VDD = 3.465V or 2.625V, VIN = 0V

-150

-5

µA

µA

VPP

Peak-to-Peak Input Voltage

0.15

1.3

V

VCMR

Common Mode Input Voltage:

NOTE 1, 2

GND + 0.5

VDD - 0.85

V

NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.

NOTE 2: Common mode voltage is defined as VIH.

TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5% OR 2.5V ± 5%, OR VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%;

TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

fMAX

Output Frequency

tPD

Propagation Delay, NOTE 1

f ≤ 200MHz

2.5

tsk(b)

Q0:Q7

Bank Skew;

NOTE 2, 6

Q8:Q15

Q16:Q23

Measured on the rising edge of VDDO/2

200

5.25

125

200

175

MHz

ns

ps

ps

ps

tsk(o)

tsk(pp)

tR

tF

odc

Output Skew; NOTE 3, 6

Part-to-Part Skew; NOTE 4, 6

Output Rise Time; NOTE 5

Output Fall Time; NOTE 5

Output Duty Cycle

Measured on the rising edge of VDDO/2

Measured on the rising edge of VDDO/2

30% to 70%

30% to 70%

f ≤ 200MHz

200

200

40%

250

ps

1

ns

800

ps

800

ps

60%

%

tEN

Output Enable Time; NOTE 5

f = 10MHz

5

ns

tDIS

Output Disable TIme; NOTE 5

f = 10MHz

4

ns

All parameters measured at 200MHz and VPPtyp unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to VDDO/2.

NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.

NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.

NOTE 4: Defined as between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER

5

ICS8344AYI-01 REV. B MAY 10, 2007

Share Link: