ICS83905AGLF View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

ICS83905AGLF

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

Integrated Device Technology 

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ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 6C. AC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions Minimum Typical Maximum Units

Using External Crystal

fMAX

Output Frequency Using External Clock

Source; NOTE 1

10

40

MHz

DC

100

MHz

odc

Output Duty Cycle

47

53

%

tsk(o) Output Skew; NOTE 2, 4

80

ps

tjit(Ø) RMS Phase Jitter (Random)

25MHz @ (Integration

Range: 100Hz-1MHz)

0.27

ps

tR/ tF

Output Rise/Fall Time

tEN

Output Enable Time; ENABLE 1

NOTE 3

ENABLE 2

20% to 80%

200

900

ps

4

cycles

4

cycles

tDIS

Output Disable Time; ENABLE 1

NOTE 3

ENABLE 2

4

cycles

4

cycles

All parameters measured at IJ fMAX using a crystal input unless noted otherwise.

Terminated at 50Ω to VDDO/2.

NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

TABLE 6D. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions Minimum Typical Maximum Units

Using External Crystal

fMAX

Output Frequency Using External Clock

Source; NOTE 1

10

40

MHz

DC

100

MHz

odc

Output Duty Cycle

48

52

%

tsk(o) Output Skew; NOTE 2, 4

80

ps

tjit(Ø) RMS Phase Jitter (Random)

25MHz @ (Integration

Range: 100Hz-1MHz)

0.14

ps

t /t

Output Rise/Fall Time

RF

tEN

Output Enable Time; ENABLE 1

NOTE 3

ENABLE 2

20% to 80%

200

800

ps

4

cycles

4

cycles

tDIS

Output Disable Time; ENABLE 1

NOTE 3

ENABLE 2

4

cycles

4

cycles

All parameters measured at IJ fMAX using a crystal input unless noted otherwise.

Terminated at 50Ω to VDDO/2.

NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER

6

ICS83905AM REV. B JULY 9, 2007

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