ICS83940DI View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS83940DI' PDF : 13 Pages View PDF
Integrated
Circuit
Systems, Inc.
ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions Minimum Typical
VIH
VIL
VPP
VCMR
Input High Voltage
LVCMOS_CLK
Input Low Voltage
LVCMOS_CLK
Peak-to-Peak Input Voltage PCLK, nPCLK
Input Common Mode Voltage;
NOTE 1, 2
PCLK, nPCLK
2.4
300
VDD - 1.4
IIN
Input Current
VOH
Output High Voltage
IOH = -20mA
1.8
VOL
Output Low Voltage
IOL = 20mA
IDD
Core Supply Current
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
Maximum
VDD
0.8
1000
VDD - 0.6
±200
0.5
25
Units
V
V
mV
V
µA
V
V
mA
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
PCLK, nPCLK;
tpLH
Propagation Delay
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
1.7
1.7
PCLK, nPCLK;
tpLH
Propagation Delay NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f > 150MHz
f > 150MHz
1.6
1.8
250
MHz
3.2
ns
3.0
ns
3.4
ns
3.3
ns
tsk(o)
Output Skew;
NOTE 3, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
150
ps
150
ps
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f ≤ 150MHz
f ≤ 150MHz
1.5
ns
1.3
ns
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f > 150MHz
f > 150MHz
1.8
ns
1.5
ns
tsk(pp)
Part-to-Part Skew;
NOTE 4, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
850
ps
750
ps
tR
Output Rise Time
tF
Output Fall Time
odc
Output Duty Cycle
0.5 to 1.8V
0.5 to 1.8V
f < 134MHz
0.3
1.2
ns
0.3
1.2
ns
45
50
55
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
83940DYI
www.icst.com/products/hiperclocks.html
5
REV. A DECEMBER 12, 2002
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