ICS8442AYLF View Datasheet(PDF) - Integrated Circuit Systems

Part Name

Description

MFG CO.

ICS8442AYLF

700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

Integrated Circuit Systems 

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Integrated

Circuit

Systems, Inc.

ICS8442

700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL

LVDS FREQUENCY SYNTHESIZER

TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

VOD

∆ VOD

VOS

∆ VOS

Differential Output Voltage

VOD Magnitude Change

Offset Voltage

VOS Magnitude Change

250

1.125

Typical

450

1.4

Maximum

600

50

1.6

50

Units

mV

mV

V

mV

TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

TEST_CLK; NOTE 1

10

25

MHz

fIN

Input Frequency XTAL1, XTAL2; NOTE 1

S_CLOCK

10

25

MHz

50

MHz

NOTE 1: For the input crystal and TEST_CLK frequency range the M value must be set for the VCO to operate within the

250MHz to 700MHz range. Using the minimum input frequency of 10MHz valid values of M are 25 ≤ M ≤ 70. Using the

maximum frequency of 25MHz valid values of M are 10 ≤ M ≤ 28.

TABLE 6. CRYSTAL CHARACTERISTICS

Parameter

Mode of Oscillation

Frequency

Equivalent Series Resistance (ESR)

Shunt Capacitance

Test Conditions

Minimum Typical Maximum

Fundamental

10

25

50

7

Units

MHz

Ω

pF

TABLE

7.

AC

CHARACTERISTICS,

V

DD

=

V

DDA

=

3.3V±5%,

TA

=

0°C

TO

85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum

F

OUT

tjit(cc)

Output Frequency

Cycle-to-Cycle Jitter; NOTE 1, 3

ij 350MHz

ƒ< 350MHz

31.25

700

18

28

27

45

tjit(per) Period Jitter, RMS; NOTE 1, 3

2.7

7

tsk(o) Output Skew; NOTE 2, 3

15

tR / tF

Output Rise/Fall Time

20% to 80%

150

650

M, N to nP_LOAD

5

tS

Setup Time S_DATA to S_CLOCK

5

S_CLOCK to S_LOAD

5

M, N to nP_LOAD

5

tH

Hold Time S_DATA to S_CLOCK

5

S_CLOCK to S_LOAD

5

odc

Output Duty Cycle

N>1

48

52

tPW

Output Pulse Width

N=1

tPeriod/2 - 150

tPeriod/2 + 150

tLOCK

PLL Lock Time

1

See Parameter Measurement Information section.

NOTE 1: Jitter performance using XTAL inputs.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Units

MHz

ps

ps

ps

ps

ps

ns

ns

ns

ns

ns

ns

%

ps

ms

8442AY

www.icst.com/products/hiperclocks.html

REV. C JULY 8, 2004

6

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