ICS8521 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS8521' PDF : 15 Pages View PDF
Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDD
Power
Core supply pin.
2
CLK
Input
Pulldown Non-inverting differential clock input.
3
nCLK
Input
Pullup Inverting differential clock input.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
4
CLK_SEL
Input
Pulldown When LOW, selects CLK, nCLK.
LVTTL / LVCMOS interface levels.
5
PCLK
Input
Pulldown Non-inverting differential LVPECL clock input.
6
nPCLK
Input
Pullup Inverting differential LVPECL clock input.
7
8
9, 16, 17,
24, 25, 32
GND
CLK_EN
VDDO
Power
Input
Power
Pullup
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow
clock input. When LOW, Q outputs are forced low, nQ outputs
are forced high. LVCMOS /LVTTL interface levels.
Output supply pins.
10, 11
nQ8, Q8
Output
Differential output pair. HSTL interface level.
12, 13
nQ7, Q7
Output
Differential output pair. HSTL interface level.
14, 15
nQ6, Q6
Output
Differential output pair. HSTL interface level.
18, 19
nQ5, Q5
Output
Differential output pair. HSTL interface level.
20, 21
nQ4, Q4
Output
Differential output pair. HSTL interface level.
22, 23
nQ3 Q3
Output
Differential output pair. HSTL interface level.
26, 27
nQ2, Q2
Output
Differential output pair. HSTL interface level.
28, 29
nQ1, Q1
Output
Differential output pair. HSTL interface level.
30, 31
nQ0, Q0
Output
Differential output pair. HSTL interface level.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8521BY
www.icst.com/products/hiperclocks.html
2
REV. D JULY 7, 2004
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