ICS8521BYT View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS8521BYT' PDF : 15 Pages View PDF
Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8521 is a low skew, 1-to-9 Differential-
to-HSTL Fanout Buffer and a member of the
HiPerClockS™ HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS8521 has two select-
able clock inputs. The CLK, nCLK pair can ac-
cept most standard differential input levels. The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for today’s
most advanced applications, such as IA64 and static RAMs.
FEATURES
• 9 HSTL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 500MHz
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.8ns (maximum)
•
V = 1.4V (maximum)
OH
• 3.3V core, 1.8V output operating supply voltages
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK
nCLK
0
PCLK
nPCLK
1
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
Q0
VDD 1
nQ0
CLK 2
24 VDDO
23 Q3
Q1
nCLK 3
22 nQ3
nQ1
Q2
CLK_SEL 4
PCLK 5
ICS8521
21 Q4
20 nQ4
nQ2
nPCLK 6
19 Q5
Q3
GND 7
nQ3
CLK_EN 8
18 nQ5
17 VDDO
Q4
9 1 0 1 1 1 2 1 3 1 4 1 5 16
nQ4
Q5
nQ5
Q6
32-Lead LQFP
nQ6
7mm x 7mm x 1.4mm Package Body
Q7
Y Package
nQ7
Top View
Q8
nQ8
8521BY
www.icst.com/products/hiperclocks.html
1
REV. D JULY 7, 2004
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