ICS853006 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
ICS853006
Integrated Circuit Systems
'ICS853006' PDF : 16 Pages View PDF
Integrated
Circuit
Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
V generated from the device is connected to the negative input.
BB
The C1 capacitor should be located as close as possible to the
input pin.
C1
0.1u
CLK_IN
VCC
PCLK
VBB
nPCLK
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Zo = 50Ω
FOUT
FIN
Zo = 50Ω
50Ω
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50Ω
VCC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Zo = 50Ω
FIN
Zo = 50Ω
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
853006AG
www.icst.com/products/hiperclocks.html
REV. A AUGUST 18, 2004
8
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