ICS853017AMT View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
ICS853017AMT
Integrated Circuit Systems
'ICS853017AMT' PDF : 12 Pages View PDF
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853017
QUAD, 1-TO-1
DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 20
2
VCC
Power
Core supply pins.
D0
Input Pulldown Non-inverting differential clock input.
3
nD0
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating.
4
D1
Input Pulldown Non-inverting differential clock input.
5
nD1
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating.
6
D2
Input Pulldown Non-inverting differential clock input.
7
nD2
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating.
8
D3
Input Pulldown Non-inverting differential clock input.
9
nD3
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating.
10
11
12, 13
VBB
VEE
nQ3, Q3
Power
Power
Output
Bias Voltage.
Negative supply pin.
Differential output pair. LVPECL interface levels.
14, 15
nQ2, Q2
Output
Differential output pair. LVPECL interface levels.
17, 18
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
19, 20
nQ0, Q0
Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
R
PULLDOWN
RVCC/2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
KΩ
KΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
D0:D3
Inputs
nD0:nD3
Outputs
Q0:Q3
nQ0:nQ3,
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential Non Inverting
1
0
HIGH
LOW
Differential to Differential Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
853017AM
www.icst.com/products/hiperclocks.html
2
REV. A APRIL 21, 2004
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