ICS8531-01 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'ICS8531-01' PDF : 18 Pages View PDF
ICS8531-01
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V and V must meet the V and
SWING
OH
PP
V input requirements. Figures 4A to 4E show interface
CMR
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK HiPerClockS
PCLK/nPCLK
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
3.3V
Zo = 50 Ohm
LVPEC L
Zo = 50 Ohm
3. 3V
R3
R4
125
125
3.3V
PCLK
nPCLK HiPerClockS
Input
R1
R2
84
84
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
LVDS
Zo = 50 Ohm
R5
100
Zo = 50 Ohm
3.3V
3.3V
R3
R4
1K
1K
C1
PCLK
C2
nPCLK
HiPerClockS
PC L K / n PC L K
R1
R2
1K
1K
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
3.3V
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R3
R4
84
84
C1
C2
R5
100 - 200
R6
100 - 200
R1
R2
125
125
3.3V
PCLK
nPCLK HiPerClockS
PCLK/nPCLK
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
IDT™ / ICS™ 1-TO-9, 3.3V LVPECL FANOUT BUFFER
10
ICS8531AY-01 REV. F APRIL 11, 2007
Share Link: 
