ICS8531-01 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'ICS8531-01' PDF : 18 Pages View PDF
ICS8531-01
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev Table Page
Description of Change
Date
4A
4C
4D
B
5
B
4 Separated LVCMOS rows into own table.
4 Changed HSTL table to Differential table.
Changed VPP value from 0.1 Min. to 0.15 Min.
Changed VCMR values from 0.13 Min, 1.3 Max. to 0.5 Min, VCC - 0.85.
5 In LVPECL table, changed VCMR values from 0.7 Min, 2.5 Max. to 0.5 Min, VCC - 0.85.
Changed VOH values from 1.9 Min., 2.3 Max. to VCC - 1.4 Min., VCC - 1.0 Max.
Changed VOL values from 1.2 Min, 1.6 Max. to VCC - 2.0 Min, VCC - 1.7 Max.
6/15/01
Changed VSWING values from 0.55 Min. to 0.6 Min.
5
Changed tpLH & tpHL rows to tPD. Values stayed same.
tR and tF values changed from 100 Min, 600 Max. to 300 Min., 700 Max.
Changed tDC row to odc. Values stayed same.
Deleted tS and tH rows.
Changed all VDDx to VCCx .
1 Changed VCCO to equal 3.3V ± 5% from 1.8V ± 0.2V.
Updated Block Diagram.
6/18/01
4C
B
4D
4
Changed VCMR value from 0.5 Min. to VEE + 0.5 Min.
5 Changed VPP values from 0.15 Min, 1.3 Max, to 03. Min, 1 Max.
Changed VCMR values from 0.5 Min., VCC - 0.85 Max. to VEE + 1.5 Min., VCC Max.
3 Udated Figure 1, CLK_EN Timing Diagram.
B
6 Updated Figure 2, Output Load Test Circuit.
6, 7 Revised labels on figures.
8/9/01
11/1/01
B
8 Added Termination for LVPECL Outputs section.
5/28/02
2 Pin Description table - VCC description changed to "Core supply pin" from
"Positive supply pin".
B
4 Power Supply Characteristics table - VCC description changed to
"Core Supply Voltage" from "Positive Supply Voltage".
10/02/02
T2
T4A
C
5
Output Load Test Circuit diagram - corrected V equation to read,
EE
VEE = -1.3V ± 0.165V from VEE = -1.3V ± 0.135V.
2 Pin Characteristics table - changed CIN 4pF max. to 4pF typical.
4 Updated Absolute Maximum Ratings.
4 Power Supply DC Characteristics table - changed IEE 70mA max. to 80mA max and
deleted 50mA typical.
7 Updated LVPECL Output Termination drawings.
8 Added Differential Clock Input Interface section.
2/2/04
9 Added LVPECL Clock Input Interface section.
10 Power Considerations - corrected Power Dissipation from 70mA to 80mA to
correspond with IEE.
Updated format throughout the data sheet.
C
T9
14 Ordering Information Table - added Lead-Free part number.
10/15/04
T4D
D
T9
5 LVPECL DC Characteristics - changed VSWING max. limit from 850mV to 1.0V.
7 Added Recommendations for Unused Input and Output Pins.
15 Ordering Information Table - added lead-free note.
6/23/06
1
Features Section - added RMS Phase Jitter bullet.
E
T5
5 AC Characteristics Table - add RMS Phase Jitter spec.
12/4/06
6 Added Additve Phase Jitter Plot.
T4D
5 LVPECL DC Characteristics Table -corrected V max. from V - 1.0V to
OH
CCO
F
VCCO - 0.9V.
4/11/07
12 - 13 Power Considerations - corrected power dissipation to reflect VOH max in Table 4D.
IDT™ / ICS™ 1-TO-9, 3.3V LVPECL FANOUT BUFFER
17
ICS8531AY-01 REV. F APRIL 11, 2007
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