ICS85310AI11L View Datasheet(PDF) - Integrated Circuit Systems

Part Name

Description

MFG CO.

ICS85310AI11L

LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER

Integrated Circuit Systems 

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Integrated

Circuit

Systems, Inc.

ICS85310I-11

LOW SKEW, 1-TO-10

DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Inputs

Outputs

CLK_EN

Selected Source

Q0:Q9

Q0:Q9

0

CLK0, nCLK0

Disabled; LOW

Disabled; HIGH

1

CLK1, nCLK1

Enabled

Enabled

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge

as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs as described

in Table 3B.

CLK0, nCLK0

CLK1, CLK1

CLK_EN

nQ0:nQ9

Q0:Q9

Disabled

Enabled

FIGURE 1. CLK_EN TIMING DIAGRAM

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

CLK0 or CLK1 nCLK0 or nCLK1

Outputs

Q0:Q9

nQ0:Q9

Input to Output Mode

Polarity

0

1

LOW

HIGH

Differential to Differential

Non Inverting

1

0

HIGH

LOW

Differential to Differential

Non Inverting

0

Biased; NOTE 1

LOW

HIGH

Single Ended to Differential Non Inverting

1

Biased; NOTE 1

HIGH

LOW

Single Ended to Differential Non Inverting

Biased; NOTE 1

0

HIGH

LOW

Single Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single Ended to Differential

Inverting

NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".

85310AYI-11

www.icst.com/products/hiperclocks.html

3

REV. E JULY 7, 2005

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