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ICS853111A View Datasheet(PDF) - Integrated Circuit Systems

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MFG CO.
'ICS853111A' PDF : 18 Pages View PDF
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Integrated
Circuit
Systems, Inc.
ICS853111A
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Zo = 50
FOUT
FIN
Zo = 50
50
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50
VCC - 2V
RTT
FOUT
3.3V
125
125
Zo = 50
FIN
Zo = 50
84
84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
853111AY
www.icst.com/products/hiperclocks.html
9
REV. B MAY 14, 2004
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