ICS8705BYLF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS8705BYLF' PDF : 17 Pages View PDF
Integrated
Circuit
Systems, Inc.
ICS8705
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
CLK1
IIH
Input High Current
nCLK1
VDD = VIN = 3.465V
VDD = VIN = 3.465V
CLK1
IIL
Input Low Current
nCLK1
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
-150
VPP
VCMR
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
0.15
GND + 0.5
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V.
Maximum
150
5
1.3
VDD - 0.85
Units
µA
µA
µA
µA
V
V
TABLE 5A.
AC
CHARACTERISTICS,
V=
DD
V=
DDA
V
DDO
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
Output Frequency
15.625
250
tpLH
Propagation Delay,
Low-to-High; NOTE 1
CLK0
CLK1, nCLK1
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
5
5
7
7.3
CLK0
PLL_SEL = 3.3V,
fREF ≤ 200MHz, Qx ÷ 1
-100
25
150
PLL_SEL = 3.3V,
t(Ø)
Static Phase Offset;
NOTE 2, 4
CLK1, nCLK1
fREF ≤ 167MHz, Qx ÷ 1
PLL_SEL = 3.3V,
fREF = 200MHz, Qx ÷ 1
-15
+ 135
285
-50
+100
250
CLK0
PLL_SEL = 3.3V,
fREF = 66MHz, Qx * 2
-150
-25
100
CLK1, nCLK1
PLL_SEL = 3.3V,
fREF = 66MHz, Qx * 2
0
150
300
tsk(o)
Output Skew;
NOTE 3, 4
CLK0
CLK1, nCLK1
PLL_SEL = 0V
PLL_SEL = 0V
65
55
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4
fOUT > 40MHz
45
tL
PLL Lock Time
1
tR / tF
Output Rise/Fall Time
400
950
43
57
odc
Output Duty Cycle
PLL x 4 mode, fin = 45MHz,
fOUT = 180MHz
47
53
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
mS
ps
%
%
8705BY
www.icst.com/products/hiperclocks.html
5
REV. G JUNE 16, 2004
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