ICS8725 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS8725' PDF : 7 Pages View PDF
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8725
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1
2
3
4
5
6
7
8
9
10
11
12
13, 28,
29
14, 15
16. 17,
24, 25
18, 19
20, 21
22, 23
26, 27
30
31
32
Name
DIV_SEL0
DIV_SEL1
REF_CLK1
nREF_CLK1
REF_CLK2
nRE2_CLK2
REF_SEL
MR
VDDI
nFB_IN
FB_IN
REF_DIV
Type
Description
Input
Input
Pulldown
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
Pulldown
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
Input Pulldown Non-inverting differential clock input.
Input Pullup Inverting differential clock input.
Input Pulldown Non-inverting differential clock input.
Input Pullup Inverting differential clock input.
Input
Input
Pulldown
Differential clock select input. When Low selects REF_CLK2 or
nREF_CLK2. When HIGH selects REF_CLK1 or nREF_CLK1.
Pulldown
Resets dividers and determine state of the outputs.
LVCMOS / LVTTL interface levels.
Power
Input and core power supply pin. Connect to 3.3V.
Input Pullup Feedback input to phase detector for regenerating clocks with "zero delay".
Input Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
Input Pulldown
VEE
nQ0,
Q0
Power
Output
Ground pins. Connect to ground.
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
VDDO
nQ1,
Q1
nQ2,
Q2
nQ3,
Q3
nQ4,
Q4
VDDA
PLL_SEL
VDDI
Power
Output
Output
Output
Output
Power
Input
Power
Pullup
Output power supply pins. Connect to 1.8V.
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
PLL power supply pin. Connect to 3.3V.
Selects between the PLL and the reference clock as the input to the
dividers. When HIGH select PLL. When LOW selects reference clock.
LVCMOS / LVTTL interface levels.
Output power supply pin. Connect to 3.3V.
8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
2
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