ICS8737-11 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS8737-11' PDF : 13 Pages View PDF
Integrated
Circuit
Systems, Inc.
ICS8737-11
LOW SKEW ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VEE
Power
Negative supply pin. Connect to ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
2
CLK_EN Power Pullup When LOW, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
3
CLK_SEL
Input
Pulldown
Clock Select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels.
4
CLK
Input Pulldown Non-inverting differential clock input.
5
nCLK
Input Pullup Inverting differential clock input.
6
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
7
nPCLK
Input Pullup Inverting differential LVPECL clock input.
8
nc
Unused
No connect.
9
MR
Input Pulldown Master reset. Resets the output divider.
10, 13, 18
VCC
Power
11, 12 nQB1, QB1 Output
Positive supply pins. Connect to 3.3V.
Differential output pair. LVPECL interface levels.
14, 15 nQB0, QB0 Output
Differential output pair. LVPECL interface levels.
16, 17 nQA1, QA1 Output
Differential output pair. LVPECL interface levels.
19, 20 nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
CLK, nCLK
Input Capacitance PCLK, nPCLK
CLK_SEL,
CLK_EN, MR
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
51
51
Maximum
4
4
Units
pF
pF
4
pF
KW
KW
8737AG-11
www.icst.com/products/hiperclocks.html
2
REV. A JULY 13, 2001
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