ICS8737AG-11T View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
ICS8737AG-11T
Integrated Circuit Systems
'ICS8737AG-11T' PDF : 13 Pages View PDF
Integrated
Circuit
Systems, Inc.
ICS8737-11
LOW SKEW ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
MR CLK_EN CLK_SEL Selected Source QA0 thru QA1 nQA0 thru nQA1 QB0 thru QB1 nQB0 thru nQB1
1
X
X
X
LOW
HIGH
LOW
HIGH
0
0
0
CLK, nCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH
0
0
1
PCLK, nPCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH
0
1
0
CLK, nCLK
Enabled
Enabled
Enabled
Enabled
0
1
1
PCLK, nPCLK
Enabled
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown if Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQA0 - nQA1,
nQB0 - nQB1
QA0 - QA1,
QB0 - QB1
Disabled
Enabled
FIGURE 1: CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK or PCLK nCLK or nPCLK
Outputs
QAx nQAx QBx nQBx
Input to Output Mode
Polarity
0
0
LOW HIGH LOW HIGH Differential to Differential Non Inverting
1
1
HIGH LOW HIGH LOW
Differential to Differential
Non Inverting
0
Biased; NOTE 1 LOW HIGH LOW HIGH Single Ended to Differential Non Inverting
1
Biased; NOTE 1 HIGH LOW HIGH LOW Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH LOW HIGH LOW Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW HIGH LOW HIGH Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring differential input to
accept single ended levels.
8737AG-11
www.icst.com/products/hiperclocks.html
3
REV. A JULY 13, 2001
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