ICS9248F-146-T View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
ICS9248F-146-T
Integrated Circuit Systems
'ICS9248F-146-T' PDF : 16 Pages View PDF
ICS9248-146
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation.
SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-146. All other clocks will continue to run while
the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that
guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to
the SDRAM clocks inside the ICS9248-146.
3. All other clocks continue to run undisturbed.
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