ICS9248YF-128 View Datasheet(PDF) - Integrated Circuit Systems
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MFG CO.
'ICS9248YF-128' PDF : 16 Pages View PDF
ICS9248-128
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an sychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
SDRAM_STOP# is synchronized by the ICS9248-128. All other clocks will continue to run while the SDRAM clocks are
disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse
width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to
the SDRAM clocks inside the ICS9248-128.
3. All other clocks continue to run undisturbed.
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