ICS9248YF-153-T View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS9248YF-153-T' PDF : 14 Pages View PDF
ICS9248-153
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-153. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-153 internally. PCICLK (0:5) clocks are stopped in a low state and
started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off
latency is one PCICLK clock.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-runningl)
CPU_STOP#
PCI_STOP#
PWR_DWN#
PCICLK
(External)
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
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