ICS9250-28 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
ICS9250-28
Integrated Circuit Systems
'ICS9250-28' PDF : 17 Pages View PDF
ICS9250-28
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit Pin#
Name
Bit 7 - Reserved
Bit 6 - Reserved
Bit 5 - Reserved
Bit 4 - Reserved
Bit 3 - Reserved
Bit 2 - Reserved
Bit 1 - Reserved
Bit 0 - Reserved
PWD Description
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Group Timing Relationship Table1
Group
CPU to SDRAM
CPU to 3V66
CPU 66MHz
SDRAM 100MHz
Offset Tolerance
-2.5ns 500ps
7.5ns 500ps
CPU 100MHz
SDRAM 100MHz
Offset Tolerance
5.0ns 500ps
5.0ns 500ps
CPU 133MHz
SDRAM 100MHz
Offset Tolerance
0.0ns 500ps
0.0ns 500ps
CPU 133MHz
SDRAM 133MHz
Offset Tolerance
3.75ns 500ps
0.0ns 500ps
SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps -3.75ns 500ps
3V66 to PCI
PCI to PCI
USB & DOT
1.5-3.5ns
0.0ns
Asynch
500ps
500ps
N/A
1.5-3.5ns
0.0ns
Asynch
500ps
500ps
N/A
1.5-3.5ns
500ps
Asynch
500ps
1.0ns
N/A
1.5 -3.5ns
0.0ns
Asynch
500ps
500ps
N/A
6
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